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Espressif Systems /ESP32-C6 /LP_I2C0 /I2C_FIFO_ST

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Interpret as I2C_FIFO_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2C_RXFIFO_RADDR 0I2C_RXFIFO_WADDR 0I2C_TXFIFO_RADDR 0I2C_TXFIFO_WADDR

Description

FIFO status register.

Fields

I2C_RXFIFO_RADDR

This is the offset address of the APB reading from rxfifo
I2C_RXFIFO_WADDR

This is the offset address of i2c module receiving data and writing to rxfifo.
I2C_TXFIFO_RADDR

This is the offset address of i2c module reading from txfifo.
I2C_TXFIFO_WADDR

This is the offset address of APB bus writing to txfifo.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data